Introduction

 

We have seen that in combinational logic the outputs are determined only by the current states of the inputs. In sequential logic, however, the outputs are determined not only by the current inputs but also by the sequence of inputs that led to the current state. In other words, the circuit has the characteristic of memory.

Figure 4.1 shows a generalized sequential system which combines combinational logic with some form of memory within a feedback path. The memory elements are devices that can store binary information; the output at any time is determined by the present inputs and the data stored in the memory elements. The information stored within the memory determines the state of the circuit at any time, while the next state of the system is determined by the present state and the inputs. Thus the operation of the arrangement is determined by the existing inputs and the sequence of inputs that preceded them.

Sequential circuits can be divided into those which are synchronous and those which are asynchronous. In synchronous systems the inputs, outputs and internal states are sampled at definite instants of time, the timing of this process being controlled by a clock signal. In such systems it is common for many circuits to be controlled by a single clock signal such that their operations are synchronized. In asynchronous systems the circuitry responds to changes in the inputs at any time. The effects of input changes thus propagate throughout the system, each circuit adding its own delay. Thus in asynchronous sequential systems, internal states and output variables can be updated at any time .

Although many electronic circuits are sequential in nature, the most common sequential building blocks are the various types of multivibrator. This classification covers circuits of many different forms which are characterized by having two outputs which are the inverse of each other, and zero, one or more inputs. The outputs are usually given the labels Q and Q. Having only these two outputs means that the circuits have only two possible output states, namely Q=1, Q=0and Q=0, Q=1. Different forms of multivibrator are defined by the behaviour of the circuits in these two states. Three basic types are possible.

 

 

 ● Bistable multivibrators in which both output states are stable. When in one state the circuit will remain in that state until an input signal causes it to change state. There are several types of bistable multivibrator but unfortunately there is no general agreement on which names should be used for these classes of device. Some engineers refer to all bistable devices as flip-flop while others use the term latch for level sensitive devices and flip-flop for edge-triggered and pulse-triggered devices (the meanings of these terms will be explained shortly). Here we will adopt the latter terminology since it gives additional information about the form of the device.

 ● Monostable multivibrators in which one state is stable and the other is meta-stable (or quasi-stable). The circuit will remain in its stable state until acted upon by an appropriate input signal, whereupon it will change to its meta-stable state. It will remain in its meta-stable state for a fixed period of time (determined by circuit parameters) and then will automatically revert to its stable state. The circuit behaves as a single pulse generator. When triggered it enters its meta-stable state, causing the outputs to change for a fixed period of time. This circuit is also known as a one-shot.

 ● Astable multivibrators in which both states are meta-stable. The circuit stays in each state for a fixed period of time (determined by circuit parameters) before switching to its other state. This produces a circuit that continually oscillates from one state to the other - a digital oscillator.

 

 

It is often useful to be able to control the operation of a latch so that the inputs can be enabled at some times and disabled at others. The circuit of Figure 4.2 provides this facility.

Two NAND gates are used to 'gate' the S and R input signals before they are applied to the latch. A third input, latch enable (EN), can be used to allow or inhibit the actions of the other inputs. When the enable signal is low, the signals S' and R' are both high regardless of the signals applied to the S and R inputs. This places the active-low input latch into its memory mode, preventing any change to its state. When the enable input is taken high, the S and R signals are inverted by the gating arrangement and then applied to the latch. Thus, when the enable is high the circuit acts as a conventional, active-high input S-R latch, but when the enable is low, the circuit ignores any signals applied to the Sand R inputs. Figure 4.3 illustrates the response of the circuit to a series of input changes. Since Q is simply the inverse of Q it is not shown in this waveform diagram.

 

 

 

Figure 4.3   Sample input and output waveforms for a gated S-R latch.

 

Another form of latch that is widely used is the gated D latch, which is also known as the transparent D latch. This circuit has two inputs D and EN, as shown in Figure 4.4.

Clearly the circuit bears a striking resemblance to that of the gated S-R latch shown in Figure 4.2, but uses a single signal D and its inverse D to act as inputs to the gating network. As before, when the enable input is low the signals fed to the latch are both high and the latch is placed in its memory mode preventing any change of state. If the enable is taken high, the D input determines the signals applied to the latch inputs S' and R'. If D is high, S' will be low and R' will be high and the latch will be set with Q=1. If D is low, S' will be high and R' will be low which will reset the latch with Q =0. Thus when the enable is high the Q output takes the present value of D, and when the enable is low the Q output will remain in its present state. The D latch may therefor be thought of as a digital equivalent of the analogue sample and hold gate described in other Example. When the enable is high the Q output follows the input data D and when the enable goes low the output remembers the value of D when the enable went low. This characteristic gives rise to the circuit being called a data latch or simply a D latch. The operation of the D latch is illustrated in Figure 4.5.

In addition to storing single bits of information, D latches are often used in groups to store words of information. It is common to combine a number of latches within a single integrated circuit to give, perhaps, four bits (a quad latch) or eight bits (an octal latch) of storage within a single device. Figure 4.6 shows an octal latch in which eight bits of data can be sampled and stored using a single enable input. When the enable input is high the outputs Y₀-Y₇ are identical to the inputs X₀-X₇. When the enable input goes low the outputs are frozen at their values when the enable went low, storing this value. This technique of 'latching' data is used extensively within microcomputers and other areas of digital electronics.

 

Figure4.4   A gated D latch.

 

Figure 4.5  Sample input and output waveforms for a gated D latch.

 

Figure 4.6   An octal data latch.

 

1.       combinational    n.组合，结合

2.       sequential       a.连续的，相继的

3.       characteristic     a.特有的，典型的，表示特性的 (+of)  n.特性，特色，特点

4.       generalized       a.广义的

5.       arrangement      n.安排,准备

6.       synchronous      a.同时的

7.       synchronous     a. 非同期的

8.       internal       a.内的,内部的  n本质,本性

9.       definite       a.明确的,确切的

10.   propagate     v.繁殖,增殖

11.   delay         v.使延期,拖延  n.延迟,耽搁

12.   update       vt.更新

13.   multivibrator   n.多谐振荡器 

14.   behaviour    n.特点，特性，状态

15.   bistable      a.双稳定的，双稳态的

16.   unfortunately  ad.不幸地

17.   sensitive     a.敏感的

18.   terminology  n.(总称)术语,专门用语

19.   monostable  a.单稳定的，单稳态的

20.   whereupon     ad.在那上面,据此

21.   meta-     pref.表示“变化”,“变换”

22.   quasi-     pref.“几乎”，“半”，“准”

23.   automatically   ad.自动地

24.   astable     a.不稳定的，非稳态的

25.   oscillate     v.摆动

26.   latch     n.锁存器

27.   facility    n.能力

28.   inhibit     vt禁止

29.   illustrate     vt.（用图，实例等）说明，阐明

30.   transparent     a.透明的，清澈的

31.   extensively     ad.广大地，广泛地

 

32.   edge-triggere    边沿触发器

33.   flip-flop        触发器

34.   one-shot        [口]只有一次的

 

 

 

 

 

1.        时序逻辑电路的特点：任一时刻的输出不但取决于该时刻的输入, 而且还与电路的原状态有关系.

2.        触发器是时序逻辑电路的基本单元, 有五种不同功能的触发器.

3.        触发器的基本特点是:  (1) 具有两个互补的输出Q与Q×   （2）具有0和1 两个稳态                 

           （3）具有触发翻转的特性          （4）具有记忆功能

4.        一种功能最简单的时序逻辑电路是触发器。

5.        多谐振荡器有双稳态的、单稳态的、无稳态的三种.

 

 

The carry propagation delay is the time required for a counter to complete its response to an input pulse. The carry time of a  ripple counter is longest when each stage is in the 1 state.

For in this situation, the next pulse must cause all previous FLIP-FLOPS to change state. Any particular binary will not respond until the preceding stage has nominally completed its transition. The clock pulse effectively “ripples” through the chain. Hence the carry time will be of the order of magnitude of the sum of the propagation delay times of all the binaries. If the chain is long, the carry time may well be longer than the interval between input pulses. In such a case ,it will not be possible to read the counter between pulses.

If  the asynchronous operation of a counter is changed so that all  FLIP –FLOPS are clocked simultaneously (synchronously) by the input pulses, the propagation delay  time may be reduced considerably.  Repetition rate is limited by the delay of any on  FLIP-FLOP plus the propagation times of any control gates required. Typically, the maximum frequency of operation of a 4-bit synchronous counter using TTL logic is 32 MHz , which is about twice that of a ripple counter. Another advantage of the synchronous counter is that no decoding spikes appear at the output since all FLIP-FLOPS change state at the same time . Hence no strobe pulse is required when decoding a synchronous counter